1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device for introducing therein an address signal in synchronization with an external clock.
2. Description of the Background Art
FIG. 13 is a timing chart showing the relation between an external clock ext.CLK and an external address ext.Add that are input to a conventional synchronous dynamic random access memory (SDRAM).
Referring to FIG. 13, the timing of introducing the external address ext.Add is defined with respect to the rising edge of the external clock ext.CLK. In FIG. 13, tIS indicates setup time, and tIH indicates hold time.
The input address passes through an input buffer including a comparator and the like, which is located at a first input stage. In the input buffer, the input address is converted into a signal INTA having an appropriate internal level. The signal INTA is latched for a fixed period in an address latch. A trigger signal of the address latch is an internal clock ZCLKF produced from the clock ext.CLK. Although depending also on the circuit characteristics of the address latch, the setup time tIS and hold time tIH are determined mainly according to the propagation characteristics of the signal INTA and internal clock ZCLKF.
The propagation characteristics of these signals depend on the distance from an address pad and a clock pad to the address latch. Accordingly, the position of the address latch within the chip is important.
FIG. 14 is a diagram illustrating the pad arrangement and memory-array arrangement of a conventional general SDRAM.
Referring to FIG. 14, the SDRAM 500 includes memory banks A to D. The memory banks A to D are arranged in two rows by two columns. Each memory bank has a row decoder RD located in the center thereof, and column decoder bands CPW located on both sides of the row decoder RD so as to correspond to respective memory arrays. More specifically, the bank A includes memory arrays 501 and 502. The bank B includes memory arrays 503 and 504. The bank C includes memory arrays 505 and 506. The bank D includes memory arrays 507 and 508.
The SDRAM 500 has a central region extending along the line connecting the respective middle points of the shorter sides of the chip. The SDRAM 500 includes an address pad train 514, a control-signal pad train 516, and a DQ pad train 518 in the central region.
The DQ pad 518 is located between the banks A and B. The address pad train 514 and control-signal pad train 516 are located between the banks C and D.
A first input stage 512 is provided corresponding to the pads receiving an input signal out of pads 510 of these pad trains. The pads of the address pad train 514 correspond to an address signal on a bit-by-bit basis. More specifically, the pads of the address pad train 514 respectively correspond to address signals A4, A3, A5, A2, A6, A1, A7, A0, A8, A10, A9, BA1, A11, BA0, A12 sequentially from its end. The address thus input from the address pad train 514 passes through the first input stage 512, and is input to an address latch circuit 538 as a signal INTA.
The control-signal pad train 516 includes a pad for receiving a clock signal CLK. The clock CLK is input through a first input stage to the address latch circuit 538 as an internal clock ZCLKF.
FIG. 15 is a diagram showing the structure of the address latch circuit 538 of FIG. 14.
Referring to FIG. 15, the address latch circuit 538 includes address latches 538.0 to 538.14 respectively corresponding to the bits of the address signal. More specifically, the address latches 538.0 to 538.12 receive address signals INTA_A0 to INTA_A12, and output signals ADD less than 0 greater than  to ADD less than 12 greater than , respectively. The address latches 538.13 and 538.14 receive address signals INTA_BA0 and INTA_BA1, and output signals BADD less than 0 greater than  and BADD less than 1 greater than , respectively.
The address latch circuit 538 further includes an inverter 540 for receiving the internal clock signal ZCLKF and generating a clock signal CLKA serving as a reference for introducing the internal address signal INTA to each address latch. The inverter 540 drives an internal node having a plurality of clock input nodes of the address latches connected thereto and thus having large load capacitance.
FIG. 16 is a circuit diagram showing the structure of the address latch 538.0 in FIG. 15.
Referring to FIG. 16, the address latch 538.0 includes an inverter 552 for receiving and inverting the clock signal CLKA, an inverter 554 for receiving and inverting the signal INTA, and P-channel MOS transistors 556, 558 and N-channel MOS transistors 560, 562 connected in series between the power supply potential and the ground potential. The P-channel MOS transistors 556 and 558 receive the output of the inverter 554 and the clock signal CLKA at their gates, respectively. The N-channel MOS transistors 560 and 562 receive the outputs of the inverters 552 and 554 at their gates, respectively.
The address latch 538.0 further includes inverters 564, 568 having their inputs connected to the drain of the N-channel MOS transistor 560, a clocked inverter 570 for receiving the output of the inverter 568 for feedback to the input of the inverter 568, and an inverter 566 for receiving the output of the inverter 564 and outputting the signal ADD. The clocked inverter 570 is activated in response to activation of the clock signal CLKA.
Referring back to FIG. 14, the address pad train 514 is arranged in line, and therefore has a long train length. Provided that all address latches are collectively located at a single location as in the address latch circuit 538, the length of a path from the first input stage to the address latch circuit 538, i.e., a transmission path of the signal INTA, is significantly different from address bit to address bit, resulting in variation in setup time and hold time among the address bits.
Note that it is also possible to arrange the address latches separately on a pad-by-pad basis. In this case, however, the propagation time of the internal clock signal ZCLKF becomes different from address bit to address bit, also resulting in variation in setup time and hold time among the address bits.
In order to solve these problems in principle, it is primarily important to reduce the length of the address pad train. One possible method thereof is to arrange the address pads in two or more trains.
However, in the general structure of FIG. 14 in which the memory banks are arranged in two rows by two columns, arranging the address pads in two trains increases the width of the peripheral circuit band extending along the line connecting the respective middle points of the shorter sides of the chip, thereby significantly increasing the length of the shorter side of the chip. As a result, the number of chips obtained per wafer is significantly reduced, resulting in increased costs of the semiconductor memory device. Therefore, arranging the address pads in multiple trains has been substantially impossible at least in a chip in which the memory banks are arranged in two rows by two columns, i.e., a chip for mass production.
Conventionally, dynamic random access memories (DRAMs) including synchronous dynamic random access memories (SDRAMs) generally have a 2n-bit storage capacity. In order to realize this capacity, the memory arrays or banks of the DRAM are generally arranged in two by two, i.e., two rows by two columns.
Developing a new DRAM with a fourfold memory capacity in a 3-year cycle is a conventional trend. However, it is becoming technically difficult to improve the memory capacity as such. In the meantime, with expansion of the information and communication industry such as widespread use of the Internet, there is an active demand on the market for the improved memory capacity. In such circumstances, a DRAM having a 2(2n+1)-bit capacity has also been developed against the conventional trend. Such a DRAM may have an irregular memory-array arrangement instead of the conventional mainstream, i.e., the arrangement in two rows by two columns.
For example, a DRAM with a 512-Mbit capacity may have memory arrays arranged in regions of three rows by three columns. The central region of the second row, second column is a region where peripheral circuitry and pads are provided, and the memory arrays are arranged so as to surround the peripheral-circuit region located in the center. In this case, because of a large width of the peripheral-circuit region, arranging the pads in multiple trains does not affect the length of the shorter side of the chip.
There have been examples in which the pads are arranged in two trains in the peripheral-circuit region. However, the address-latch arrangement for suppressing variation in setup time and hold time among the address bits has not specifically been discussed. A method for improving the characteristics of the setup time and hold time, and distribution of latched signals have not been studied.
In addition to the example in which the memory banks are arranged in two rows by two columns, there have been examples for improving the propagation characteristics of the signals entering the address latches. In these examples, a plurality of signals INTA are prevented from becoming adjacent to each other so as not to interfere with each other, the buffer size of the signal INTA is made different from address to address, and the like. However, the delay time resulting from parasitic resistance and parasitic capacitance of the interconnection is different from address to address, necessitating generation of the difference in arrival time to the address latch.
It is an object of the present invention to improve, in a semiconductor memory device operating in synchronization with an external clock, the characteristics of the setup time and hold time by optimizing the arrangement of address latches particularly in the case where memory arrays are arranged so as to surround the central region of the chip where peripheral circuitry is provided.
In summary, according to the present invention, a semiconductor memory device formed in a memory region of a main surface of a semiconductor substrate includes a plurality of terminal groups, a clock terminal, an address latch circuit, and a plurality of memory blocks.
The plurality of terminal groups are each located collectively in a central region of the memory region, and receive respective allocated bits of an external address signal. The clock terminal is provided in the central region, and receives an external clock signal. The address latch circuit is provided in the central region at a substantially equal distance from the plurality of terminal groups, and latches the address signal according to the clock signal. The plurality of memory blocks are provided in a peripheral region surrounding the central region in the memory region, and receive and output data according to an output of the address latch circuit.
According to another aspect of the present invention, a semiconductor memory device formed in a memory region of a main surface of a semiconductor substrate includes a plurality of terminal groups, a clock terminal, a plurality of address latch circuits, and a plurality of memory blocks.
The plurality of terminal groups are each located collectively in a central region of the memory region, and receive respective allocated bits of an external address signal. The clock terminal is provided in the central region, and receives an external clock signal. The plurality of address latch circuits are each provided in the central region at a substantially equal distance from the plurality of terminal groups, and latch the address signal according to the clock signal. The plurality of memory blocks are provided in a peripheral region surrounding the central region in the memory region, and receive and output data according to respective outputs of the plurality of address latch circuits.
According to a further aspect of the present invention, a semiconductor memory device includes a plurality of terminals, an address latch circuit, a plurality of memory blocks, and a plurality of interconnections.
The plurality of terminals receive respective allocated bits of an external address signal. The address latch circuit latches the address signal. The plurality of memory blocks receive and output data according to an output of the address latch circuit. The plurality of interconnections are respectively provided on a plurality of paths for transmitting the respective address bits from the plurality of terminals to the address latch circuit. Each of the plurality of interconnections has its width and its distance to an adjacent interconnection determined according to a path length from the corresponding terminal to the address latch circuit.
Accordingly, a primary advantage of the present invention is that respective path lengths from terminals receiving an address to an address latch circuit can be averaged, and variation in setup time and hold time can be reduced.
Another advantage of the present invention is that the variation in setup time and hold time can further be reduced according to the respective path lengths from the terminals to the address latch circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.